The present invention relates generally to integrated circuit devices and more particularly to systems and methods for dynamic element matching in data converters, such as digital-to-analog converters.
Sigma delta modulators (SDMs) are devices used in data converters, such as analog-to-digital (A/D) converters, where the SDM performs noise shaping functions. SDMs may be first order, second order, or jth order, where j is a positive integer. For example, a typical first order sigma delta modulator comprises a filter, such as an integrator circuit, which receives an analog input signal as well as a feedback signal, and a quantizer, such as a flash A/D converter, which quantizes the filter output signal to create a digital output. In the simplest form, the quantizer may be a single bit A/D, such as a comparator circuit. A digital to analog (D/A) converter creates an analog representation of the current digital output and provides this as an analog feedback signal to the filter. Multiple order sigma delta modulators may include a series of n filters in a forward path, each filtering the output of the previous filter and receiving an analog feedback signal based on the digitized output of the modulator, where the first filter operates on the analog input signal to be converted and the feedback signal. Multi-bit or multi-level sigma delta modulators provide multi-bit digital or quantized outputs, wherein the analog to digital converter provides a multi-bit digital output representative of the input signal. In this case, the feedback D/A converter is a multi-bit converter as well.
Whereas single-bit sigma delta modulators can achieve good linearity, linearity performance and stability are generally not as good as in multi-bit sigma delta modulators. In this regard, the linearity of a multi-bit SDM is essentially limited by the linearity of the D/A converter, particularly nonlinearity due to mismatch of D/A internal components, which causes a distortion in the modulator. This distortion is typically found as harmonics of the input signal, which is a serious problem for some applications, such as audio data conversion. One approach for dealing with the non-linearity problems for multi-bit data converters involves dynamic element matching (DEM), which operates to transform the non-linearity error caused by D/A element mismatch into random noise, in combination with noise-shaping by changing the bit pattern of data such that most of the noise falls outside the signal band of interest. This out-of-band noise can then be filtered out, such as by decimation filtering. In general, the D/A element mismatch is thus converted from a static error into a wide-bandwidth noise by selecting different D/A elements to represent a digital input code at different times. Such DEM techniques may be employed in an SDM feedback path to vary the selection of mismatched components in the D/A converter in response to the quantized (e.g., digital input) signal.
Data Weighted Averaging (DWA) is one of the conventional DEM algorithms and has been widely used. However, DWA algorithms suffer from the production of unintended tone components in the output, sometimes referred to as idle channel tones. This problem is particularly troublesome for static (e.g., DC) or slowly changing input signals, and/or for low oversampling ratios (e.g., less than or equal to 8), wherein the modulator creates a repetitive pattern, which appears as a tonal component in the output spectrum. This degrades usable system range, sometimes measured as Spurious Free Dynamic Range (SFDR). Accordingly, there is a need for improved D/A converters and DEM systems therefor, as well as methods by which tones are dispersed and SFDR is improved in systems employing D/A converters with mismatched circuit elements.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. The invention relates to systems and methods for dynamic element matching (DEM) in which D/A converter elements are selected according to a DEM code and a digital input code, where a current DEM code is generated according to a previous DEM code, the digital input code, and a dither code.
One aspect of the invention provides a DEM system for selecting D/A converter elements according to a digital input code, which comprises a dither system generating a dither code and a DEM code system generating a current DEM code according to a previous DEM code, the dither code, and the digital input code. A switching system is provided, which generates select signals for selecting D/A elements according to the digital input code and one of the current DEM code and the previous DEM code. In one example, the switching system comprises a barrel shifter circuit, and the dither system generates the dither code as a pseudo-random code, as a code representative of quantization noise associated with a quantizer, or as a code representative of a non-zero constant value.
The DEM code system may comprise an adder circuit which sums the dither code and the digital input code to generate an intermediate sum code, as well as an accumulator which sums the intermediate sum code and the previous DEM code to generate the current DEM code. In one implementation, the adder may be configured to selectively sum the dither code with the digital input code or to set the intermediate sum code to be equal to the digital input code according to a cycle status associated with the previous DEM code. For example, the DEM code system may comprise a cycle detector circuit receiving the previous DEM code and providing a corresponding cycle status signal, as well as a gate circuit receiving the cycle status signal and the dither code, which selectively provides the dither code to the adder circuit according to the cycle status signal.
Another aspect of the invention provides a sigma delta modulator, comprising one or more filters receiving an input signal and an analog feedback signal, which provides a filtered output signal, as well as a quantizer that provides a quantized output signal according to the filtered output signal. A D/A converter receives the quantized output signal as a digital input code and provides an analog feedback signal, using D/A elements selected according to the quantized output signal. The modulator also comprises a DEM system comprising a dither system to generate a dither code and a DEM code system to generate a current DEM code according to a previous DEM code, the dither code, and the quantized output signal. The DEM system also comprises a switching system, which generates select signals for selecting D/A elements according to the quantized output signal and one of the current DEM code and the previous DEM code.
Yet another aspect of the invention provides data conversion systems, such as A/D, D/A, or other converters, including one or more D/A converters comprising a plurality of selectable D/A elements, and a DEM system for varying the selection of D/A elements of the D/A converter. The DEM system comprises a dither system generating a dither code, a DEM code system generating a current DEM code according to a previous DEM code, the dither code, and the digital input code, and a switching system generating select signals for selecting D/A elements according to the digital input code and one of the current DEM code and the previous DEM code.
Still another aspect of the invention provides a method for selecting D/A converter elements according to a digital input code. The method comprises receiving a digital input code, generating a dither code, generating a current DEM code according to a previous DEM code, the dither code, and the digital input code, and selecting D/A elements according to the digital input code and one of the current DEM code and the previous DEM code. In one implementation, the method further comprises converting the digital input code to a binary input code, wherein the current DEM code is generated according to the previous DEM code, the dither code, and the binary input code. The dither code may be generated as a pseudo-random code, as a code representative of quantization noise associated with a quantizer, or as a code representative of a non-zero constant value.
Generation of the current DEM code may involve determining a cycle status associated with the previous DEM code, selectively summing the dither code and the digital input code to generate an intermediate sum code according to the cycle status, and summing the intermediate sum code and the previous DEM code to generate the current DEM code. In this example, selectively summing the dither code and the digital input code may comprise summing the dither code and the digital input code to generate the intermediate sum code if the cycle status is a first status, and setting the intermediate sum code equal to the digital input code if the cycle status is not the first status.
The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed.